Lam Research 10-K 2019-06-30

UNITED STATES

SECURITIES AND EXCHANGE COMMISSION

Washington, D.C. 20549

For the fiscal year ended June 30, 2019

OR

For the transition period from to .

Commission file number: 0-12933

Registrant’s telephone number, including area code: (510) 572-0200

Securities registered pursuant to Section 12(b) of the Act:

Securities registered pursuant to Section 12(g) of the Act:

None

(Title of class)

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Indicate by check mark if the registrant is a well-known seasoned issuer, as defined in Rule 405 of the Securities Act. Yes ☒ No ☐

Indicate by check mark if the registrant is not required to file reports pursuant to Section 13 or Section 15(d) of the Act. Yes ☐ No ☒

Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. Yes ☒ No ☐

Indicate by check mark whether the registrant has submitted electronically every Interactive Data File required to be submitted pursuant to Rule 405 of Regulation S-T (§ 232.405 of this chapter) during the preceding 12 months (or for such shorter period that the registrant was required to submit such files). Yes ☒ No ☐

Indicate by check mark whether the registrant is a large accelerated filer, an accelerated filer, a non-accelerated filer, a smaller reporting company, or an emerging growth company. See the definitions of “large accelerated filer,” “accelerated filer”, “smaller reporting company”, and “emerging growth company” in Rule 12b-2 of the Exchange Act.

If an emerging growth company, indicate by check mark if the registrant has elected not to use the extended transition period for complying with any new or revised financial accounting standards provided pursuant to Section 13(a) of the Exchange Act. ☐

Indicate by check mark whether the registrant is a shell company (as defined in Rule 12b-2 of the Act). Yes ☐ No ☒

The aggregate market value of the Registrant’s Common Stock, $0.001 par value, held by non-affiliates of the Registrant, as of December 23, 2018, the last business day of the most recently completed second fiscal quarter, was $15,363,329,674. Common Stock held by each officer and director and by each person who owns 5% or more of the outstanding Common Stock has been excluded from this computation based on the assumption that such persons may be deemed to be affiliates. This determination of affiliate status is not necessarily a conclusive determination of such status for other purposes.

As of August 15, 2019, the Registrant had 144,532,998 outstanding shares of Common Stock.

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Documents Incorporated by Reference

Parts of the Registrant’s Proxy Statement for the Annual Meeting of Stockholders expected to be held on or about November 5, 2019, are incorporated by reference into Part III of this Form 10-K. Except as expressly incorporated by reference herein, the Registrant’s proxy statement shall not be deemed to be part of this report.

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LAM RESEARCH CORPORATION

2019 ANNUAL REPORT ON FORM 10-K

TABLE OF CONTENTS

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PART I

CAUTIONARY STATEMENT REGARDING FORWARD-LOOKING STATEMENTS

With the exception of historical facts, the statements contained in this discussion are forward-looking statements, which are subject to the safe harbor provisions created by the Private Securities Litigation Reform Act of 1995. Certain, but not all, of the forward-looking statements in this report are specifically identified as forward-looking, by use of phrases and words such as “believe,” “estimated,” “anticipate,” “expect,” “probable,” “intend,” “plan,” “aim,” “may,” “should,” “could,” “would,” “will,” “continue,” and other future-oriented terms. The identification of certain statements as “forward-looking” does not mean that other statements not specifically identified are not forward-looking. Forward-looking statements include but are not limited to statements that relate to: trends and opportunities in the global economic environment and the semiconductor industry; the anticipated levels of, and rates of change in, margins, market share, served addressable market, capital expenditures, research and development expenditures, international sales, revenue (actual and/or deferred), operating expenses and earnings generally; management’s plans and objectives for our current and future operations and business focus; volatility in our quarterly results; customer and end user requirements and our ability to satisfy those requirements; customer capital spending and their demand for our products and services, and the reliability of indicators of change in customer spending and demand; the effect of variability in our customers’ business plans or demand for our equipment and services; changes in demand for our products and in our market share resulting from, among other things, any changes in our customers’ proportion of capital expenditure (with respect to certain technology inflections); hedging transactions; debt or financing arrangements; our competition, and our ability to defend our market share and to gain new market share; our ability to obtain and qualify alternative sources of supply; changes in state, federal and international tax laws, our estimated annual tax rate and the factors that affect our tax rates; anticipated growth or decline in the industry and the total market for wafer fabrication equipment, our growth relative thereto and the resulting impact on us from such growth or decline; the success of joint development and collaboration relationships with customers, suppliers, or others; outsourced activities; the role of component suppliers in our business; our leadership and competency, and our ability to facilitate innovation; our ability to continue to, including the underlying factors that, create sustainable differentiation; the resources invested to comply with evolving standards and the impact of such efforts; legal and regulatory compliance; the estimates we make, and the accruals we record, in order to implement our critical accounting policies (including but not limited to the adequacy of prior tax payments, future tax benefits or liabilities, and the adequacy of our accruals relating to them); our investment portfolio; our access to capital markets; uses of, payments of, and impact of interest rate fluctuations on, our debt; our intention to pay quarterly dividends and the amounts thereof, if any*;* our ability and intention to repurchase our shares; credit risks; controls and procedures; recognition or amortization of expenses; our ability to manage and grow our cash position; our strategic relevance with our customers; our ability to scale our operations to respond to changes in our business; the value of our patents; the materiality of potential losses arising from legal proceedings; the probability of making payments under our guarantees; and the sufficiency of our financial resources or liquidity to support future business activities (including but not limited to operations, investments, debt service requirements, dividends, and capital expenditures). Such statements are based on current expectations and are subject to risks, uncertainties, and changes in condition, significance, value, and effect, including without limitation those discussed below under the heading “Risk Factors” within Item 1A and elsewhere in this report and other documents we file from time to time with the Securities and Exchange Commission (“SEC”), such as our quarterly reports on Form 10-Q and our current reports on Form 8-K. Such risks, uncertainties, and changes in condition, significance, value, and effect could cause our actual results to differ materially from those expressed in this report and in ways not readily foreseeable. Readers are cautioned not to place undue reliance on these forward-looking statements, which speak only as of the date hereof and are based on information currently and reasonably known to us. We do not undertake any obligation to release the results of any revisions to these forward-looking statements, which may be made to reflect events or circumstances that occur after the date of this report or to reflect the occurrence or effect of anticipated or unanticipated events.

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Incorporated in 1980, Lam Research Corporation (“Lam Research,” “Lam,” “we,” “our,” “us,” or the “Company”) is a Delaware corporation, headquartered in Fremont, California. We maintain a network of facilities throughout Asia, Europe, and the United States in order to meet the needs of our dynamic customer base.

Additional information about Lam Research is available on our website at www.lamresearch.com. The content on any website referred to in this Form 10-K is not a part of or incorporated by reference in this Form 10-K unless expressly noted.

Our Annual Report on Form 10-K, Quarterly Reports on Forms 10-Q, Current Reports on Forms 8-K, Proxy Statements and all other filings we make with the SEC are available on our website, free of charge, as soon as reasonably practical after we file them with or furnish them to the SEC and are also available online at the SEC’s website at www.sec.gov.

The Lam Research logo, Lam Research, and all product and service names used in this report are either registered trademarks or trademarks of Lam Research Corporation or its subsidiaries in the United States and/or other countries. All other marks mentioned herein are the property of their respective holders.

We are a global supplier of innovative wafer fabrication equipment and services to the semiconductor industry. We have built a strong global presence with core competencies in areas like nanoscale applications enablement, chemistry, plasma and fluidics, advanced systems engineering and a broad range of operational disciplines. Our products and services are designed to help our customers build smaller, faster, and better performing devices that are used in a variety of electronic products, including mobile phones, personal computers, servers, wearables, automotive vehicles, and data storage devices. Our vision is to realize full value from natural technology extensions of our Company.

Our customer base includes leading semiconductor memory, foundry, and integrated device manufacturers (“IDMs”) that make products such as non-volatile memory (“NVM”), dynamic random-access memory (“DRAM”), and logic devices. We aim to increase our strategic relevance with our customers by contributing more to their continued success. Our core technical competency is integrating hardware, process, materials, software, and process control enabling results on the wafer.

Semiconductor manufacturing, our customers’ business, involves the complete fabrication of multiple dies or integrated circuits (“ICs”) on a wafer. This involves the repetition of a set of core processes and can require hundreds of individual steps. Fabricating these devices requires highly sophisticated process technologies to integrate an increasing array of new materials with precise control at the atomic scale. Along with meeting technical requirements, wafer processing equipment must deliver high productivity and be cost-effective.

Demand from cloud computing (the “Cloud”), the Internet of Things (“IoT”), and other markets is driving the need for increasingly powerful and cost-efficient semiconductors. At the same time, there are growing technical challenges with traditional two-dimensional scaling. These trends are driving significant inflections in semiconductor manufacturing, such as the increasing importance of vertical scaling strategies like three-dimensional (“3D”) architectures as well as multiple patterning to enable shrinks.

We believe we are in a strong position with our leadership and competency in deposition, etch, and clean to facilitate some of the most significant innovations in semiconductor device manufacturing. Several factors create opportunity for sustainable differentiation for us: (i) our focus on research and development, with several on-going programs relating to sustaining engineering, product and process development, and concept and feasibility; (ii) our ability to effectively leverage cycles of learning from our broad installed base; (iii) our collaborative focus with semi-ecosystem partners; (iv) our ability to identify and invest in the breadth of our product portfolio to meet technology inflections; and (v) our focus on delivering our multi-product solutions with a goal to enhance the value of Lam’s solutions to our customers.

We also address processes for back-end wafer-level packaging (“WLP”), which is an alternative to traditional wire bonding and can offer a smaller form factor, increased interconnect speed and bandwidth, and lower power consumption, among other benefits. In addition, our products are well-suited for related markets that rely on

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semiconductor processes and require production-proven manufacturing capability, such as complementary metal-oxide-semiconductor image sensors (“CIS”) and micro-electromechanical systems (“MEMS”).

Our Customer Support Business Group (“CSBG”) provides products and services to maximize installed equipment performance, predictability, and operational efficiency. We offer a broad range of services to deliver value throughout the lifecycle of our equipment, including customer service, spares, upgrades, and refurbishment of our deposition, etch, and clean products. Many of the technical advances that we introduce in our newest products are also available as upgrades, which provide customers with a cost-effective strategy for extending the performance and capabilities of their existing wafer fabrication lines. Service offerings include addressing productivity needs for our customers including, but not limited to, system uptime or availability optimization, throughput improvements, and defect reduction. Additionally, within CSBG, our Reliant product line offers new and refurbished non-leading-edge products in Clean, Deposition, and Etch markets for those applications that do not require the most advanced wafer processing capability.

Products

Deposition Processes and Product Families

Deposition processes create layers of dielectric (insulating) and metal (conducting) materials used to build a semiconductor device. Depending on the type of material and structure being made, different techniques are employed. Electrochemical deposition creates the copper wiring (interconnect) that links devices in an integrated circuit (“IC” or “chip”). Plating of copper and other metals is also used for TSV and WLP applications. Tiny tungsten connectors and thin barriers are made with the precision of chemical vapor deposition and atomic layer deposition, which adds only a few layers of atoms at a time. Plasma-enhanced CVD, high-density plasma CVD, and ALD are used to form the critical insulating layers that isolate and protect all of these electrical structures. Lastly, post-deposition treatments such as ultraviolet thermal processing are used to improve dielectric film properties.

ALTUS® Product Family

Tungsten deposition is used to form conductive features such as contacts, vias, and wordlines on a chip. These features are small, often narrow, and use only a small amount of metal, so minimizing resistance and achieving complete fill can be difficult. At these nanoscale dimensions, even slight imperfections can impact device

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performance or cause a chip to fail. Our ALTUS® systems combine CVD and ALD technologies to deposit the highly conformal films needed for advanced tungsten metallization applications. The Multi-Station Sequential Deposition architecture enables nucleation layer formation and bulk CVD fill to be performed in the same chamber (“in situ”). PNL®, our ALD technology, is used in the deposition of tungsten nitride films to achieve high step coverage with reduced thickness relative to conventional barrier films.

SABRE® Product Family

Copper deposition lays down the electrical wiring for most semiconductor devices. Even the smallest defect - say, a microscopic pinhole or dust particle - in these conductive structures can impact device performance, from loss of speed to complete failure. The SABRE*®* ECD product family, which helped pioneer the copper interconnect transition, offers the precision needed for copper damascene manufacturing in logic and memory. System capabilities include cobalt deposition for logic applications and copper deposition directly on various liner materials, which is important for next-generation metallization schemes. For advanced WLP applications, such as forming conductive bumps and redistribution layers, and for filling TSVs, the SABRE® 3D family combines Lam’s SABRE Electrofill® technology with additional innovation to deliver the high-quality films needed at high productivity. The modular architecture can be configured with multiple plating and pre/post-treatment cells, providing flexibility to address a variety of packaging applications.

SOLA® Product Family

Dielectric materials designed to meet the insulation requirements of logic chips often have attributes that make them unusually difficult to use. These films are easily damaged and vulnerable to losing some of their insulating capability, which can lead to poor device performance. To enable these applications, some films can be stabilized - and others enhanced to improve device performance - using specialized post-deposition film treatments available with Lam’s SOLA® UVTP product family. SOLA® products offer process flexibility through independent control of temperature, wavelength, and intensity at each station of the wafer path, enabled by Multi-Station Sequential Processing architecture.

SPEED® Product Family

Dielectric gapfill processes deposit critical insulation layers between conductive and/or active areas by filling openings of various aspect ratios between conducting lines and between devices. With advanced devices, the structures being filled can be very tall and narrow. As a result, high-quality dielectric films are especially important due to the ever-increasing possibility of cross-talk and device failure. Our SPEED*®* HDP-CVD products provide a multiple dielectric film solution for high-quality gapfill with industry-leading throughput and reliability. SPEED*®* products have excellent particle performance, and their design allows large batch sizes between cleans and faster cleans.

Striker® Product Family

The latest memory, logic, and imaging devices require extremely thin, highly conformal dielectric films for continued device performance improvement and scaling. For example, ALD films are critical for spacer-based multiple patterning schemes where the spacers help define critical dimensions, as well as for insulating liners and gapfill in high aspect ratio features, which have little tolerance for voids and even the smallest defect. The Striker® single-wafer ALD products provide dielectric film solutions for these challenging requirements through application-specific material, process and hardware options that deliver film technology and defect performance.

VECTOR® Product Family

Dielectric film deposition processes are used to form some of the most difficult-to-produce insulating layers in a semiconductor device, including those used in the latest transistors and 3D structures. In some applications, these films require dielectric films to be exceptionally smooth and defect free since slight imperfections are multiplied greatly in subsequent layers. Our VECTOR® PECVD products are designed to provide the performance and flexibility needed to create these enabling structures within a wide range of challenging device applications. As a result of its design, VECTOR® produces superior thin film quality, along with exceptional within-wafer and wafer-to-wafer uniformity.

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Etch Processes and Product Families

Etch processes help create chip features by selectively removing both dielectric (insulating) and metal (conducting) materials that have been added during deposition. These processes involve fabricating increasingly small, complex, and narrow features using many types of materials. The primary technology, reactive ion etch, bombards the wafer surface with ions (charged particles) to remove material. For the smallest features, atomic-layer etching (“ALE”) removes a few atomic layers of material at a time. While conductor etch processes precisely shape critical electrical components like transistors, dielectric etch forms the insulating structures that protect conducting parts. Etch processes also create the tall, column-like features used, for example, in TSVs that link chips together and in MEMS.

Flex® Product Family

Dielectric etch carves patterns in insulating materials to create barriers between the electrically conductive parts of a semiconductor device. For advanced devices, these structures can be extremely tall and thin and involve complex, sensitive materials. Slight deviations from the target feature profile - even at the atomic level - can negatively affect electrical properties of the device. To precisely create these challenging structures, our Flex® product family offers differentiated technologies and application-focused capabilities for critical dielectric etch applications. Uniformity, repeatability, and tunability are enabled by a unique multi-frequency, small-volume, confined plasma design. Flex® offers in situ multi-step etch and continuous plasma capability that delivers high productivity with low defectivity.

Kiyo® Product Family

Conductor etch helps shape the electrically active materials used in the parts of a semiconductor device. Even a slight variation in these miniature structures can create an electrical defect that impacts device performance. In fact, these structures are so tiny that etch processes are pushing the boundaries of the basic laws of physics and chemistry. Our Kiyo® product family delivers the high-performance capabilities needed to precisely and consistently form these conductive features with high productivity. Proprietary Hydra technology in Kiyo*®* products improves critical dimension (“CD”) uniformity by correcting for incoming pattern variability, and atomic-scale variability control with production-worthy throughput is achieved with plasma-enhanced ALE capability.

Syndion® Product Family

Plasma etch processes used to remove silicon and other materials deep into the wafer are collectively referred to as deep silicon etch. These may be deep trenches for CMOS image sensor pixel isolation, trenches for power and other devices, TSVs, and other high aspect ratio features. These are created by etching through multiple materials sequentially, where each new material involves a change in the etch process. The Syndion® etch product family is optimized for deep silicon etch, providing the fast process switching with depth and cross-wafer uniformity control required to achieve precision etch results. The systems support both conventional single-step etch and rapidly alternating process, which minimizes damage and delivers precise depth uniformity.

Versys® Metal Product Family

Metal etch processes play a key role in connecting the individual components that form an IC, such as forming wires and electrical connections. These processes can also be used to drill through metal hardmasks that pattern features too small for conventional masks, allowing continued shrinking of feature dimensions. To enable these critical etch steps, the Versys® Metal product family provides high-productivity capability on a flexible platform. Superior CD and profile uniformity are enabled by a symmetrical chamber design with independent process tuning features.

Clean Processes and Product Families

Clean techniques are used between manufacturing steps to clear away particles, contaminants, residues and other unwanted material that could later lead to defects and to prepare the wafer surface for subsequent processing. Wet processing technologies can be used for wafer cleaning and etch applications. Plasma bevel cleaning is used to enhance die yield by removing unwanted materials from the wafer’s edge that could impact the device area.

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Coronus® Product Family

Bevel cleaning removes unwanted masks, residues, and films from the edge of a wafer between manufacturing steps. If not cleaned, these materials become defect sources. For instance, they can flake off and re-deposit on the device area during subsequent processes. Even a single particle that lands on a critical part of a device can ruin the entire chip. By inserting bevel clean processes at strategic points, these potential defect sources can be eliminated and more functional chips produced. By combining the precise control and flexibility of plasma with technology that protects the active die area, the Coronus® bevel clean family cleans the wafer’s edge to enhance die yield. The systems provide active die area protection by using plasma processing with proprietary confinement technology. Applications include post-etch, pre- and post-deposition, pre-lithography, and metal film removal to prevent arcing during plasma etch or deposition steps.

DV-Prime®, Da Vinci®, EOS®, and SP Series Product Families

Wafer cleaning is performed repeatedly during semiconductor device manufacturing and is a critical process that affects product yield and reliability. Unwanted microscopic materials - some no bigger than the tiny structures themselves - need to be cleaned effectively. At the same time, these processes must selectively remove residues that are chemically similar to the device films. For advanced WLP, the wet clean steps used between processes that form the package and external wiring have surprisingly complex requirements. These processes are called on to completely remove specific materials and leave other fragile structures undisturbed. In IoT products that include power devices, MEMS and image sensors, there is a unique requirement for wafer backside wet etch to uniformly thin the silicon wafer while protecting the device side of the wafer.

Based on our pioneering single-wafer spin technology, the DV-Prime® and Da Vinci® products provide the process flexibility needed with high productivity to address a wide range of wafer cleaning steps throughout the manufacturing process flow. As the latest of Lam’s wet clean products, EOS® delivers exceptionally low on-wafer defectivity and high throughput to address progressively demanding wafer cleaning applications, including emerging 3D structures. With a broad range of process capability, our SP Series products deliver cost-efficient, production-proven wet clean and silicon wet etch solutions for challenging WLP and IoT applications.

Mass Metrology Processes and Product

Mass metrology measures the change in mass following deposition, etch, and clean processes to enable monitoring and control of these often-repeated core manufacturing steps. For design components like thin film stacks, high aspect-ratio structures, and complex 3D architectures, optical techniques are limited in their ability to measure accurately the thick, deep, or otherwise visually obscured features. Measuring the change in mass for these applications provides a straightforward high-precision solution for monitoring and control of the critical features in advanced device structures, where there is often little tolerance for variation. Our line of high-precision mass metrology systems provides in-line monitoring and control of deposition, etch, and clean steps in real time - recording minute changes in mass to enable advanced detection of potential process excursions.

Metryx*®* Product Family

Metryx*®* mass metrology systems provide high precision in-line mass measurement for semiconductor wafer manufacturing. Nearly all semiconductor processes (e.g., deposition, etch and clean) either add or remove materials from the wafer. Measuring mass change of a wafer before and after a process therefore is a simple and direct means of monitoring and controlling the process. It is widely used to identify production wafer trends and excursions as they occur, allowing corrections to be implemented quickly to prevent further yield loss. It is particularly useful for ultra-thin, ultra-thick and opaque films, and complex 3D geometries of newer chip designs, where traditional metrology and inspection techniques are ineffective.

The Metryx® mass metrology systems are available as both platform-integrated modules and as stand-alone systems. Key applications include high aspect ratio etch (DRAM cell, 3D NAND channel hole, carbon mask open), conformal and ALD sidewall deposition, horizontal processing (recess etch, fill), film density monitoring, and wafer cleaning/polymer removal.

Fiscal Periods Presented

All references to fiscal years apply to our fiscal years, which ended June 30, 2019, June 24, 2018, and June 25, 2017.

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Research and Development

The market for semiconductor capital equipment is characterized by rapid technological change and product innovation. Our ability to achieve and maintain our competitive advantage depends in part on our continued and timely development of new products and enhancements to existing products. Accordingly, we devote a significant portion of our personnel and financial resources to research and development (“R&D”) programs and seek to maintain close and responsive relationships with our customers and suppliers.

We believe current challenges for customers at various points in the semiconductor manufacturing process present opportunities for us. We expect to continue to make substantial investments in R&D to meet our customers’ product needs, support our growth strategy and enhance our competitive position.

Marketing, Sales, and Service

Our marketing, sales, and service efforts are focused on building long-term relationships with our customers and targeting product and service solutions designed to meet their needs. These efforts are supported by a team of product marketing and sales professionals as well as equipment and process engineers who work closely with individual customers to develop solutions for their wafer processing needs. We maintain ongoing service relationships with our customers and have an extensive network of service engineers in place throughout the United States, China, Europe, Japan, Korea, Southeast Asia, and Taiwan. We believe that comprehensive support programs and close working relationships with customers are essential to maintaining high customer satisfaction and our competitiveness in the marketplace.

We provide standard warranties for our systems. The warranty provides that systems will be free from defects in material and workmanship and will conform to agreed-upon specifications. The warranty is limited to repair of the defect or replacement with new or like-new equivalent goods and is valid when the buyer provides prompt notification within the warranty period of the claimed defect or non-conformity and also makes the items available for inspection and repair. We also offer extended warranty packages to our customers to purchase as desired.

International Sales

A significant portion of our sales and operations occur outside the United States and, therefore, may be subject to certain risks, including but not limited to tariffs and other barriers; difficulties in staffing and managing non-U.S. operations; adverse tax consequences; foreign currency exchange rate fluctuations; changes in currency controls; compliance with U.S. and international laws and regulations, including U.S. export restrictions; and economic and political conditions. Any of these factors may have a material adverse effect on our business, financial position, and results of operations and cash flows. For geographical reporting, revenue is attributed to the geographic location in which the customers’ facilities are located. Refer to Note 19 of our Consolidated Financial Statements, included in Item 8 of this report, for the attribution of revenue by geographic region.

Long-lived Assets

Refer to Note 19 of our Consolidated Financial Statements, included in Item 8 of this report, for information concerning the geographic locations of long-lived assets.

Customers

Our customers include all of the world’s leading semiconductor manufacturers. Customers continue to establish joint ventures, alliances, and licensing arrangements which have the potential to positively or negatively impact our competitive position and market opportunities. Customers accounting for greater than 10% of total revenues in fiscal year 2019 included Micron Technology, Inc.; Samsung Electronics Company, Ltd.; SK hynix Inc.; and Toshiba, Inc. Customers accounting for greater than 10% of total revenues in fiscal year 2018 included Intel Corporation; Micron Technology, Inc.; Samsung Electronics Company, Ltd.; SK hynix Inc.; and Toshiba, Inc. Customers accounting for greater than 10% of total revenues in fiscal year 2017 included Micron Technology, Inc.; Samsung Electronics Company, Ltd.; SK hynix Inc.; Taiwan Semiconductor Manufacturing Company, Ltd; and Toshiba, Inc.

A material reduction in orders from our customers could adversely affect our results of operations and projected financial condition. Our business depends upon the expenditures of semiconductor manufacturers. Semiconductor manufacturers’ businesses, in turn, depend on many factors, including their economic capability,

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the current and anticipated market demand for ICs, and the availability of equipment capacity to support that demand.

Backlog

In general, we schedule production of our systems based upon our customers’ delivery requirements and forecasts. In order for a system to be included in our backlog, the following conditions must be met: (1) we have received a written customer request that has been accepted, (2) we have an agreement on prices and product specifications, and (3) there is a scheduled shipment within the next 12 months. In order for spares and services to be included in our backlog, the following conditions must be met: (1) we have received a written customer request that has been accepted and (2) delivery of products or provision of services is anticipated within the next 12 months. Where specific spare parts and customer service purchase contracts do not contain discrete delivery dates, we use volume estimates at the contract price and over the contract period, not to exceed 12 months, in calculating backlog amounts. Our policy is to revise our backlog for order cancellations and to make adjustments to reflect, among other things, changes in spares volume estimates and customer delivery date changes. As of June 30, 2019, and June 24, 2018, our backlog was $1.6 billion and $2.0 billion, respectively. Generally, orders for our products and services are subject to cancellation by our customers with limited penalties. Because some orders are received and shipped in the same quarter and because customers may change delivery dates and cancel orders, our backlog at any particular date is not necessarily indicative of business volumes or actual revenue levels for succeeding periods.

Manufacturing

Our manufacturing operations mainly consist of assembling and testing components, sub-assemblies, and modules that are then integrated into finished systems prior to shipment to or at the location of our customers. The assembly and testing of our products is conducted predominately in cleanroom environments.

We have agreements with third parties to outsource certain aspects of our manufacturing, production warehousing, and logistics functions. These outsourcing contracts provide us more flexibility to scale our operations up or down in a timely and cost-effective manner, enabling us to respond quickly to any changes in our business. We believe that we have selected reputable providers and have secured their performance on terms documented in written contracts. However, it is possible that one or more of these providers could fail to perform as we expect, and such failure could have an adverse impact on our business and have a negative effect on our operating results and financial condition. Overall, we believe we have effective mechanisms to manage risks associated with our outsourcing relationships. Refer to Note 16 of our Consolidated Financial Statements, included in Item 8 of this report, for further information concerning our outsourcing commitments, reported as a component of purchase obligations.

Certain components and sub-assemblies that we include in our products may only be obtained from a single supplier. We believe that, in many cases, we could obtain and qualify alternative sources to supply these products. Nevertheless, any prolonged inability to obtain these components could have an adverse effect on our operating results and could unfavorably impact our customer relationships.

Environmental Matters

We are subject to a variety of governmental regulations related to the management of hazardous materials that we use in our business operations. We are currently not aware of any pending notices of violations, fines, lawsuits, or investigations arising from environmental matters that would have a material effect on our business. We believe that we are generally in compliance with these regulations and that we have obtained (or will obtain or are otherwise addressing) all necessary environmental permits to conduct our business. Nevertheless, the failure to comply with present or future regulations could result in fines being imposed on us, require us to suspend production or cease operations, or cause our customers to not accept our products. These regulations could require us to alter our current operations, to acquire significant additional equipment, or to incur substantial other expenses to comply with environmental regulations. Our failure to control the use, sale, transport, or disposal of hazardous substances could subject us to future liabilities.

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Employees

As of August 15, 2019, we had approximately 10,700 regular employees globally. Although we have employment-related agreements with a number of key employees, these agreements do not guarantee continued service. Each of our employees is required to comply with our policies relating to maintaining the confidentiality of our non-public information. As noted previously, we outsource certain aspects of our manufacturing, field service, production warehousing, and logistics functions to provide us more flexibility to scale our operations up or down in a timely and cost-effective manner, enabling us to respond quickly to any changes in our business.

In the semiconductor and semiconductor capital equipment industries, competition for highly skilled employees is intense. Our future success depends, to a significant extent, upon our continued ability to attract and retain qualified employees, particularly in the R&D and customer support functions.

Competition

The semiconductor capital equipment industry is characterized by rapid change and is highly competitive throughout the world. To compete effectively, we invest significant financial resources targeted to strengthen and enhance our product and services portfolio and to maintain customer service and support locations globally. Semiconductor manufacturers evaluate capital equipment suppliers in many areas, including but not limited to process performance, productivity, defect control, customer support, and overall cost of ownership, which can be affected by many factors such as equipment design, reliability, software advancements, and similar factors. Our ability to succeed in the marketplace depends upon our ability to maintain existing products and introduce product enhancements and new products that meet customer requirements on a timely basis. In addition, semiconductor manufacturers must make a substantial investment to qualify and integrate new capital equipment into semiconductor production lines. As a result, once a semiconductor manufacturer has selected a particular supplier’s equipment and qualified it for production, the manufacturer generally maintains that selection for that specific production application and technology node as long as the supplier’s products demonstrate performance to specification in the installed base. Accordingly, we may experience difficulty in selling to a given customer if that customer has qualified a competitor’s equipment. We must also continue to meet the expectations of our installed base of customers through the delivery of high-quality and cost-efficient spare parts in the presence of competition from third-party spare parts providers.

We face significant competition with all of our products and services. Our primary competitor in the dielectric and metals deposition market is Applied Materials, Inc. For ALD and PECVD, we also compete against ASM International and Wonik IPS. In the etch market, our primary competitors are Applied Materials, Inc.; Hitachi, Ltd.; and Tokyo Electron, Ltd., and our primary competitors in the wet clean market are Screen Holding Co., Ltd.; Semes Co., Ltd.; and Tokyo Electron, Ltd.

We face competition from a number of established and emerging companies in the industry. We expect our competitors to continue to improve the design and performance of their current products and processes, to introduce new products and processes with enhanced price/performance characteristics, and to provide more comprehensive offerings of products. If our competitors make acquisitions or enter into strategic relationships with leading semiconductor manufacturers, or other entities, covering products similar to those we sell, our ability to sell our products to those customers could be adversely affected. Strategic investments to encourage local semiconductor manufacturing and supply chain in China could increase competition from domestic equipment manufacturers in China. There can be no assurance that we will continue to compete successfully in the future.

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Patents and Licenses

Our policy is to seek patents on inventions relating to new or enhanced products and processes developed as part of our ongoing research, engineering, manufacturing, and support activities. We currently hold a number of U.S. and foreign patents covering various aspects of our products and processes. Our patents, which cover material aspects of our past and present core products, have current durations ranging from approximately one to twenty years. We believe that, although the patents we own and may obtain in the future will be of value, they alone will not determine our success. Our success depends principally upon our research and development, engineering, marketing, support, and delivery skills. However, in the absence of patent protection, we may be vulnerable to competitors who attempt to imitate our products, manufacturing techniques, and processes. In addition, other companies and inventors may receive patents that contain claims applicable or similar to our products and processes. The sale of products covered by patents of others could require licenses that may not be available on terms acceptable to us, or at all. For further discussion of legal matters, see Item 3, “Legal Proceedings,” of this report.

Information about our Executive Officers

As of August 15, 2019, the executive officers of Lam Research were as follows:

Timothy M. Archer has been our president and chief executive officer since December 2018. Prior to this, he served as our president and chief operating officer, from January 2018 to November 2018. Mr. Archer joined us in June 2012 as our executive vice president, chief operating officer. Prior to joining us, he spent 18 years at Novellus Systems, Inc., (“Novellus”) in various technology development and business leadership roles, including most recently as chief operating officer from January 2011 to June 2012; executive vice president of Worldwide Sales, Marketing, and Customer Satisfaction from September 2009 to January 2011; and executive vice president of the PECVD and Electrofill Business Units from November 2008 to September 2009. His tenure at Novellus also included assignments as senior director of technology for Novellus Systems Japan from 1999 to 2001 and senior director of technology for the Electrofill Business Unit from April 2001 to April 2002. He started his career in 1989 at Tektronix, where he was responsible for process development for high-speed bipolar ICs. Mr. Archer completed the Program for Management Development at the Harvard Graduate School of Business and earned a B.S. degree in applied physics from the California Institute of Technology.

Douglas R. Bettinger is our executive vice president, chief financial officer, and chief accounting officer with responsibility for Finance, Tax, Treasury, Information Technology, and Investor Relations. Prior to joining the Company in 2013, Mr. Bettinger served as senior vice president and chief financial officer of Avago Technologies from 2008 to 2013. From 2007 to 2008, he served as vice president of Finance and corporate controller at Xilinx, Inc., and from 2004 to 2007, he was chief financial officer at 24/7 Customer, a privately held company. Mr. Bettinger worked at Intel Corporation from 1993 to 2004, where he held several senior-level finance positions, including corporate planning and reporting controller and Malaysia site operations controller. Mr. Bettinger earned an M.B.A. degree in finance from the University of Michigan and a B.S. degree in economics from the University of Wisconsin in Madison.

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Richard A. Gottscho is our executive vice president, chief technology officer, a position he has held since May 2017. Dr. Gottscho previously served as executive vice president, Global Products Group beginning in August 2010; and group vice president and general manager, Etch Businesses beginning in March 2007**.** He joined us in January 1996 and has held various director and vice president roles spanning across deposition, etch, and clean products. Prior to joining us, he was a member of Bell Laboratories for 15 years, where he headed research departments in electronics materials, electronics packaging, and flat panel displays. In 2016, Dr. Gottscho was elected to the U.S. National Academy of Engineering. He is the recipient of many awards, including the American Vacuum Society’s Peter Mark Memorial Award, the Plasma Science and Technology Division Prize, the Dry Process Symposium Nishizawa Award, and the Tegal Thinker Award. He is a fellow of the American Physical and American Vacuum Societies. He has authored numerous papers, patents, and lectures, and has served on editorial boards of peer-reviewed technical publications and program committees for major conferences in plasma science and engineering. He served as vice-chair of a National Research Council study on plasma science. Dr. Gottscho earned Ph.D. and B.S. degrees in physical chemistry from the Massachusetts Institute of Technology and Pennsylvania State University, respectively.

Kevin D. Jennings is our senior vice president, global operations, a position he has held since February 2018 in which he is responsible for worldwide manufacturing, supply chain, logistics, and facilities. Prior to that time, he had been group vice president, global operations beginning in June 2013; and vice president, strategic development, beginning in June 2012. Prior to our acquisition of Novellus in June 2012, he held a variety of executive roles covering engineering, business development, marketing, product line general management, and operations at Novellus. Mr. Jennings has over 30 years of experience in the semiconductor capital equipment industry that includes KLA-Tencor and began in 1986 at Applied Materials. He earned an M.B.A. from Pepperdine University and an undergraduate degree in electrical engineering technology from DeVry University.

Patrick J. Lord is our senior vice president and general manager of the Customer Support Business Group, a position he has held since December 2016. Previously, Dr. Lord held the position of group vice president and deputy general manager of the Global Products Group from September 2013 to December 2016. He served as the head of the Direct Metals, GapFill, Surface Integrity Group, and Integrated Metals (“DGSI”) Business Units between June 2012 and September 2013. Prior to our acquisition of Novellus in June 2012, Dr. Lord was senior vice president and general manager of the DGSI Business Units at Novellus. Additionally, Dr. Lord held the position of senior vice president of Business Development and Strategic Planning. He joined Novellus in 2001 and held a number of other positions, including executive vice president and general manager of the CMP Business Unit, senior director of Business Development, senior director of Strategic Marketing, and acting vice president of Corporate Marketing. Before joining Novellus, Dr. Lord spent six years at KLA-Tencor Corporation (“KLA-Tencor”) in various product marketing and management roles. He earned his Ph.D., M.S., and B.S. degrees in mechanical engineering from the Massachusetts Institute of Technology.

Scott G. Meikle is our senior vice president of Global Customer Operations, a position he has held since September 2017. Before joining us, he was an independent consultant for a year and director, special projects at Micron Technology, Inc. for seven months. Prior to that time, he spent over five and a half years at Inotera Memories, Inc., most recently as its president from August 2012 to December 2015. Dr. Meikle started his career in process R&D and advanced to various leadership roles in business operations across multiple geographies for Micron Technology, and has over 25 years of experience in the memory devices sector of the semiconductor industry. He earned his Ph.D. and M. Eng. degrees in engineering physics from Shizuoka University and McMaster University, respectively, and a B.S. degree in physics from the University of Calgary.

Sarah A. O’Dowd is our senior vice president, chief legal officer and secretary. She joined us in September 2008 as group vice president and chief legal officer, responsible for general legal matters, intellectual property and ethics, and compliance. In addition to her Legal function, in April 2009 she was appointed vice president of Human Resources and served in this dual capacity through May 2012. Prior to joining us, she was vice president and general counsel for FibroGen, Inc., from February 2007 until September 2008. Until February 2007, Ms. O’Dowd was a shareholder in the law firm of Heller Ehrman LLP for more than 20 years, practicing in the areas of corporate securities, governance, and mergers and acquisitions for a variety of clients, principally publicly traded high-technology companies. She served in a variety of leadership and management roles at Heller Ehrman, including managing partner of the Silicon Valley and San Diego offices, member of the firm’s Policy Committee, and, as head of the firm’s business practice groups, a member of the firm’s Executive Committee. Ms. O’Dowd earned her J.D. and M.A. degrees in communications from Stanford Law School and Stanford University, respectively, and her B.A. degree in mathematics from Immaculata College.

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Vahid Vahedi is our senior vice president and general manager of the Etch Business Unit, a position he has held since February 2018. Prior to that time, he was group vice president of the Etch product group since March 2012. Previously, he served as vice president of Etch Business Product Management and Marketing, vice president of Dielectric Etch, vice president of Conductor and 3DIC Etch, and director of Conductor Etch Technology Development. He joined us in 1995. He earned his Ph.D., M.S., and B.S. degrees in electrical engineering and computer science from the University of California at Berkeley.

Sesha Varadarajan is our senior vice president and general manager of the Deposition Business Unit, a position he has held since February 2018. Prior that time, he was group vice president of the Deposition product group since September 2013. Previously, he served as the head of the PECVD/Electrofill Business Unit between June 2012 and September 2013. Prior to our acquisition of Novellus in June 2012, Mr. Varadarajan was senior vice president and general manager of Novellus’ PECVD and Electrofill Business Units. He joined Novellus in 1999 as a process engineer with the Electrofill Business Unit and held various roles in that business unit before being appointed director of technology in 2004. Between 2006 and 2008, he worked in the PECVD Business Unit, initially as director of technology, until being promoted to product general manager. In 2009, he returned to the Electrofill Business Unit as vice president and general manager. In mid-2011, he was promoted to senior vice president and general manager, where he was also responsible for the PECVD Business Unit. Mr. Varadarajan earned an M.S. degree in manufacturing engineering and material science from Boston University and a B.S. degree in mechanical engineering from the University of Mysore.

In addition to the other information in this Annual Report on Form 10-K (“2019 Form 10-K”), the following risk factors should be carefully considered in evaluating us and our business because such factors may significantly impact our business, operating results, and financial condition. As a result of these risk factors, as well as other risks discussed in our other SEC filings, our actual results could differ materially from those projected in any forward-looking statements. No priority or significance is intended by, nor should be attached to, the order in which the risk factors appear.

The Semiconductor Capital Equipment Industry Is Subject to Variability and Periods of Rapid Growth or Decline; We Therefore Face Risks Related to Our Strategic Resource Allocation Decisions

The semiconductor capital equipment industry has historically been characterized by rapid changes in demand. The industry environment has moved toward being more characterized by variability across segments and customers, accentuated by consolidation within the industry. Variability in our customers’ business plans may lead to changes in demand for our equipment and services, which could negatively impact our results. The variability in our customers’ investments during any particular period is dependent on several factors, including but not limited to electronics demand, economic conditions (both general and in the semiconductor and electronics industries), industry supply and demand, prices for semiconductors, and our customers’ ability to develop and manufacture increasingly complex and costly semiconductor devices. The changes in demand may require our management to adjust spending and other resources allocated to operating activities.

During periods of rapid growth or decline in demand for our products and services, we face significant challenges in maintaining adequate financial and business controls, management processes, information systems, and procedures for training, assimilating, and managing our workforce, and in appropriately sizing our supply chain infrastructure and facilities, work force, and other components of our business on a timely basis. If we do not adequately meet these challenges during periods of increasing or declining demand, our gross margins and earnings may be negatively impacted.

We continuously reassess our strategic resource allocation choices in response to the changing business environment. If we do not adequately adapt to the changing business environment, we may lack the infrastructure and resources to scale up our business to meet customer expectations and compete successfully during a period of growth, or we may expand our capacity too rapidly and/or beyond what is appropriate for the actual demand environment, resulting in excess fixed costs.

Especially during transitional periods, resource allocation decisions can have a significant impact on our future performance, particularly if we have not accurately anticipated industry changes. Our success will depend, to a

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significant extent, on the ability of our executive officers and other members of our senior management to identify and respond to these challenges effectively.

Future Declines in the Semiconductor Industry, and the Overall World Economic Conditions on Which It Is Significantly Dependent, Could Have a Material Adverse Impact on Our Results of Operations and Financial Condition

Our business depends on the capital equipment expenditures of semiconductor manufacturers, which in turn depend on the current and anticipated market demand for integrated circuits. With the consolidation of customers within the industry, the semiconductor capital equipment market may experience rapid changes in demand driven both by changes in the market generally and the plans and requirements of particular customers. The economic, political, and business conditions occurring nationally, globally, or in any of our key sales regions, which are often unpredictable, have historically impacted customer demand for our products and normal commercial relationships with our customers, suppliers, and creditors. Additionally, in times of economic uncertainty, our customers’ budgets for our products, or their ability to access credit to purchase them, could be adversely affected. This would limit their ability to purchase our products and services. As a result, changing economic, political or business conditions can cause material adverse changes to our results of operations and financial condition, including but not limited to:

Fluctuating levels of investment by semiconductor manufacturers may materially affect our aggregate shipments, revenues, operating results, and earnings. Where appropriate, we will attempt to respond to these fluctuations with cost management programs aimed at aligning our expenditures with anticipated revenue streams, which sometimes result in restructuring charges. Even during periods of reduced revenues, we must continue to invest in R&D and maintain extensive ongoing worldwide customer service and support capabilities to remain competitive, which may temporarily harm our profitability and other financial results.

Our Revenues and Operating Results Are Variable

Our revenues and operating results may fluctuate significantly from quarter to quarter or year to year due to a number of factors, not all of which are in our control. We manage our expense levels based in part on our expectations of future revenues. Because our operating expenses are based in part on anticipated future revenues, and a certain amount of those expenses are relatively fixed, a change in the timing of recognition of revenue and/or the level of gross profit from a small number of transactions can unfavorably affect operating results in a particular quarter or year. Factors that may cause our financial results to fluctuate unpredictably include but are not limited to:

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None.

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Our executive offices and principal operating and R&D facilities are located in Fremont and Livermore, California; Tualatin, Oregon; and Villach, Austria. The majority of the Fremont and Livermore facilities are held under operating leases expiring in 2020 and 2021. The Villach facilities are held under capital leases expiring in calendar year 2021. Our Fremont, Livermore, and Villach leases include options to renew or purchase the facilities. In addition, we lease or own properties for our service, technical support, and sales personnel throughout the United States, China, Europe, Japan, Korea, Southeast Asia, and Taiwan and lease or own manufacturing facilities located in Ohio and Korea. The Company owns two properties in Fremont, as well as the majority of the Tualatin facilities. Our facilities lease obligations are subject to periodic increases. We believe that our existing facilities are well-maintained and in good operating condition.

While we are not currently party to any legal proceedings that we believe are material, we are either a defendant or plaintiff in various actions that have arisen from time to time in the normal course of business, including intellectual property claims. We accrue for a liability when it is both probable that a liability has been incurred and the amount of the loss can be reasonably estimated. Significant judgment is required in both the determination of probability and the determination as to whether a loss is reasonably estimable. These accruals are reviewed at least quarterly and adjusted to reflect the effects of negotiations, settlements, rulings, advice of legal counsel, and other information and events pertaining to a particular matter. To the extent there is a reasonable possibility that the losses could exceed the amounts already accrued, we believe that the amount of any such additional loss would be immaterial to our business, financial condition, and results of operations.

Not applicable.

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PART II

Stock Information

Our Common Stock is traded on the Nasdaq Global Select MarketSM under the symbol “LRCX.” As of August 15, 2019, we had 401 stockholders of record.

Dividends

Our Board of Directors has declared quarterly dividends since April 2014. Our intent to continue to pay quarterly dividends is subject to capital availability and periodic determinations by our Board of Directors that cash dividends are in the best interest of our stockholders and are in compliance with all laws and agreements applicable to the declaration and payment of cash dividends by us. During fiscal year 2019, our quarterly dividend was $1.10 per share.

Repurchase of Company Shares

In November 2018, the Board of Directors authorized management to repurchase up to an additional $5.0 billion of Common Stock on such terms and conditions as it deems appropriate. These repurchases can be conducted on the open market or as private purchases and may include the use of derivative contracts with large financial institutions, in all cases subject to compliance with applicable law. This repurchase program has no termination date and may be suspended or discontinued at any time. Funding for this share repurchase program may be through a combination of cash on hand, cash generation, and borrowings. As of June 30, 2019, we have purchased approximately $2.0 billion of shares under this authorization, $0.5 billion via open market trading and $1.5 billion utilizing accelerated share repurchase arrangements.

Accelerated Share Repurchase Agreements

On June 4, 2019, we entered into four separate accelerated share repurchase agreements (collectively, the "June 2019 ASR") with two financial institutions to repurchase a total of $750 million of Common Stock. We took an initial delivery of approximately 3.1 million shares, which represented 75% of the prepayment amount divided by our closing stock price on June 4, 2019. The total number of shares received under the June 2019 ASR will be based upon the average daily volume weighted average price of our Common Stock during the repurchase period, less an agreed upon discount. Final settlement of the June 2019 ASR is anticipated to occur no later than November 20, 2019.

On January 31, 2019, we entered into two separate accelerated share repurchase agreements (collectively, the "January 2019 ASR") with two financial institutions to repurchase a total of $760 million of Common Stock. We took an initial delivery of approximately 3.3 million shares, which represented 75% of the prepayment amount divided by our closing stock price on January 30, 2019. The total number of shares received under the January 2019 ASR was based upon the average daily volume weighted average price of our Common Stock during the repurchase period, less an agreed upon discount. Final settlement of the agreements occurred during May 2019, resulted in the receipt of approximately 0.8 million additional shares, which yielded a weighted-average share price of approximately $182.32 for the transaction period.

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Share repurchases, including those under the repurchase program, were as follows:

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Cumulative Five-Year Return

The graph below compares Lam Research Corporation’s cumulative five-year total shareholder return on Common Stock with the cumulative total returns of the Nasdaq Composite index, the Standard & Poor’s (“S&P”) 500 index, and the Philadelphia Semiconductor Sector Index. The graph tracks the performance of a $100 investment in our Common Stock and in each of the indices (with the reinvestment of all dividends) for the five years ended June 30, 2019.

*$100 invested on June 29, 2014 in stock or June 30, 2014 in index, including reinvestment of dividends. Indexes calculated on month-end basis.

Copyright © 2019 Standard & Poor’s, a division of S&P Global. All rights reserved.

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The following discussion of our financial condition and results of operations contains forward-looking statements, which are subject to risks, uncertainties, and changes in condition, significance, value, and effect. Our actual results could differ materially from those anticipated in the forward-looking statements as a result of certain factors, including but not limited to those discussed in “Risk Factors” and elsewhere in this 2019 Form 10-K and other documents we file from time to time with the Securities and Exchange Commission. (See “Cautionary Statement Regarding Forward-Looking Statements” in Part I of this 2019 Form 10-K.)

Management’s Discussion and Analysis of Financial Condition and Results of Operations (“MD&A”) provides a description of our results of operations and should be read in conjunction with our Consolidated Financial Statements and accompanying Notes to Consolidated Financial Statements included in Part II, Item 8 of this 2019 Form 10-K. MD&A consists of the following sections:

Executive Summary provides a summary of the key highlights of our results of operations and our management’s assessment of material trends and uncertainties relevant to our business.

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Results of Operations provides an analysis of operating results.

Critical Accounting Policies and Estimates discusses accounting policies that reflect the more significant judgments and estimates used in the preparation of our Consolidated Financial Statements.

Liquidity and Capital Resources provides an analysis of cash flows, contractual obligations, and financial position.

Executive Summary

Lam Research Corporation is a global supplier of innovative wafer fabrication equipment and services to the semiconductor industry. We have built a strong global presence with core competencies in areas like nanoscale applications enablement, chemistry, plasma and fluidics, advanced systems engineering and a broad range of operational disciplines. Our products and services are designed to help our customers build smaller, faster, and better performing devices that are used in a variety of electronic products, including mobile phones, personal computers, servers, wearables, automotive vehicles, and data storage devices.

Our customer base includes leading semiconductor memory, foundry, and integrated device manufacturers that make products such as NVM, DRAM, and logic devices. We aim to increase our strategic relevance with our customers by contributing more to their continued success. Our core technical competency is integrating hardware, process, materials, software, and process control enabling results on the wafer.

Semiconductor manufacturing, our customers’ business, involves the complete fabrication of multiple dies or integrated circuits on a wafer. This involves the repetition of a set of core processes and can require hundreds of individual steps. Fabricating these devices requires highly sophisticated process technologies to integrate an increasing array of new materials with precise control at the atomic scale. Along with meeting technical requirements, wafer processing equipment must deliver high productivity and be cost-effective.

Demand from the Cloud, IoT, and other markets is driving the need for increasingly powerful and cost-efficient semiconductors. At the same time, there are growing technical challenges with traditional scaling. These trends are driving significant inflections in semiconductor manufacturing, such as the increasing importance of vertical 3D scaling strategies as well as multiple patterning to enable shrinks.

We believe we are in a strong position with our leadership and competency in deposition, etch, and clean to facilitate some of the most significant innovations in semiconductor device manufacturing. Several factors create opportunity for sustainable differentiation for us: (i) our focus on research and development, with several on-going programs relating to sustaining engineering, product and process development, and concept and feasibility; (ii) our ability to effectively leverage cycles of learning from our broad installed base; (iii) our collaborative focus with ecosystem partners; and (iv) our focus on delivering our multi-product solutions with a goal to enhance the value of Lam’s solutions to our customers.

Despite recent semiconductor capital investment volatility, over the longer term, we believe that technology inflections in our industry, including 3D device scaling, multiple patterning, process flow, and advanced packaging chip integration, will lead to an increase in our served addressable market for our products and services in deposition, etch, and clean. While there could be continued variability in the near-term, we believe that demand for our products and services will increase faster than overall spending on wafer fabrication equipment, as the proportion of customers’ capital expenditures rises in these technology inflection areas, and as we gain market share.

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The following table summarizes certain key financial information for the periods indicated below:

Fiscal year 2019 revenue decreased 13% compared to fiscal year 2018, reflecting lower customer demand for semiconductor equipment. Gross margin as a percentage of revenue decreased primarily due to lower factory utilization. The decrease in operating expenses in fiscal year 2019 compared to fiscal year 2018 was mainly driven by lower employee-related costs and amortization related to intangibles acquired through business combinations, partially offset by restructuring charges.

Fiscal year 2018 revenue increased 38% compared to fiscal year 2017, reflecting an increase in technology and capacity investments by our customers. Gross margin as a

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Investments

We maintain an investment portfolio of various holdings, types, and maturities. As of June 30, 2019, our mutual funds are classified as trading securities. Investments classified as trading securities are recorded at fair value based upon quoted market prices. Any material differences between the cost and fair value of trading securities is recognized as “Other income (expense)” in our Consolidated Statement of Operations. All of our other investments are classified as available-for-sale and consequently are recorded in the Consolidated Balance Sheets at fair value with unrealized gains or losses reported as a separate component of accumulated other comprehensive income, net of tax.

Interest Rate Risk

Fixed-Income Securities

Our investments in various interest-earning securities carry a degree of market risk for changes in interest rates. At any time, a sharp rise in interest rates could have a material adverse impact on the fair value of our fixed-income investment portfolio. Conversely, declines in interest rates could have a material adverse impact on interest income for our investment portfolio. We target a capital preservation-focused investment policy, which focuses on the safety and preservation of our capital by limiting default risk, market risk, reinvestment risk, and concentration risk. The following table presents the hypothetical fair values of fixed-income securities that would result from selected potential decreases and increases in interest rates. Market changes reflect immediate hypothetical parallel shifts in the yield curve of plus or minus 50 basis points (“BPS”), 100 BPS, and 150 BPS. The hypothetical fair values as of June 30, 2019,were as follows:

We mitigate default risk by investing in high credit quality securities and by positioning our portfolio to respond appropriately to a significant reduction in a credit rating of any investment issuer or guarantor. The portfolio includes only marketable securities with active secondary or resale markets to achieve portfolio liquidity and maintain a prudent amount of diversification.

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Long-Term Debt

As of June 30, 2019, we had $4.5 billion in principal amount of fixed-rate long-term debt outstanding, with a fair value of $5.7 billion. The fair value of our Notes is subject to interest rate risk, market risk, and other factors due to the convertible feature, as applicable. Generally, the fair value of Notes will increase as interest rates fall and decrease as interest rates rise. Additionally, the fair value of the 2041 Notes will increase as our Common Stock price increases and decrease as our Common Stock price decreases. The interest and market value changes affect the fair value of our Notes but do not impact our financial position, cash flows, or results of operations due to the fixed nature of the debt obligations. We do not carry the Notes at fair value, but present the fair value of the principal amount of our Notes for disclosure purposes.

Equity Price Risk

Publicly Traded Securities

The values of our investments in publicly traded securities, including mutual funds related to our obligations under our deferred compensation plans, are subject to market price risk. The following table presents the hypothetical fair values of our publicly traded securities that would result from potential decreases and increases in the price of each security in the portfolio. Potential fluctuations in the price of each security in the portfolio of plus or minus 10%, 15%, or 25% were selected based on potential near-term changes in those security prices. The hypothetical fair values as of June 30, 2019, were as follows:

Foreign Currency Exchange (“FX”) Risk

We conduct business on a global basis in several major international currencies. As such, we are potentially exposed to adverse as well as beneficial movements in foreign currency exchange rates. The majority of our revenues and expenses are denominated in U.S. dollars. However, we are exposed to foreign currency exchange rate fluctuations primarily related to revenues denominated in Japanese yen and euro-denominated and Korean won-denominated expenses.

We enter into foreign currency forward contracts to minimize the short-term impact of exchange rate fluctuations on certain foreign currency denominated monetary assets and liabilities, primarily cash, third-party accounts receivable, accounts payable, and intercompany receivables and payables. In addition, we hedge certain anticipated foreign currency cash flows, primarily on revenues denominated in Japanese yen and expenses denominated in euro and Korean won.

To protect against adverse movements in value of anticipated revenues denominated in Japanese yen and expenses denominated in euro and Korean won, we enter into foreign currency forward and option contracts that generally expire within 12 months and no later than 24 months. The option contracts include collars, an option strategy that is comprised of a combination of a purchased put option and a written call option with the same expiration dates and Japanese yen notional amounts but with different strike prices. These foreign currency hedge contracts are designated as cash flow hedges and are carried on our balance sheet at fair value, with the effective portion of the contracts’ gains or losses included in accumulated other comprehensive income (loss) and subsequently recognized in earnings in the same period the hedged revenue and/or expense is recognized. We also enter into foreign currency forward contracts to hedge the gains and losses generated by the remeasurement of certain non-U.S.-dollar denominated monetary assets and liabilities, primarily cash, third-party accounts receivable, accounts payable, and intercompany receivables and payables. The change in fair value of these balance sheet hedge contracts is recorded into earnings as a component of other income (expense), net, and offsets the change in fair value of the foreign currency denominated monetary assets and liabilities also recorded in other income (expense), net, assuming the hedge contract fully covers the hedged items. The notional amount and unrealized gain of our outstanding forward and option contracts that are

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designated as cash flow hedges, as of June 30, 2019, are shown in the table below. This table also shows the change in fair value of these cash flow hedges assuming a hypothetical foreign currency exchange rate movement of plus or minus 10 percent and plus or minus 15 percent.

The notional amount and unrealized loss of our outstanding foreign currency forward contracts that are designated as balance sheet hedges, as of June 30, 2019, are shown in the table below. This table also shows the change in fair value of these balance sheet hedges, assuming a hypothetical foreign currency exchange rate movement of plus or minus 10 percent and plus or minus 15 percent. These changes in fair values would be offset in other income (expense), net, by corresponding change in fair values of the foreign currency denominated monetary assets and liabilities, assuming the hedge contract fully covers the intercompany and trade receivable balances.

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Interest Rate Contracts

Interest rate risk is present with both fixed- and floating-rate debt. Interest rate swap agreements designated as fair value hedges are used to mitigate our exposure to changes in the fair value of fixed-rate debt resulting from fluctuations in benchmark interest rates. Accordingly, benchmark interest rate fluctuations impact the fair value of our fixed-rate debt, which are offset by corresponding changes in the fair value of the swap agreements. Interest rate swaps may also be used to adjust interest rate exposures when appropriate, based on market conditions, and for qualifying hedges, the interest differential of swaps is included in interest expense. During the fiscal year ended June 26, 2016, we entered into a series of interest rate contracts with a total notional value of $400 million where we received fixed rates and paid variable rates based on certain benchmark interest rates. Such interest rate swap arrangements were designated as fair value hedges of the fair value of the underlying debt instrument.

The following table shows the change in fair value of these fair value hedges, assuming a hypothetical benchmark interest rate movement of plus or minus 10 BPS and plus or minus 15 BPS.

Interest rate risk is also present on anticipated issuances of debt. We manage our interest rate exposure on anticipated issuances of debt through forward-starting interest rate swap agreements. Forward-starting interest rate swap agreements designated as cash flow hedges are used to mitigate our exposure to changes in future interest payments that results from fluctuations in benchmark interest rates prior to the issuance of the debt. Accordingly, benchmark interest rate fluctuations impact the interest cash flows of the Company’s anticipated debt issuances, which are offset by corresponding changes in the fair value of the forward-starting interest rate swap agreements. During the fiscal year ended June 26, 2016, we entered into and settled a series of forward-starting interest rate swap agreements associated with our June 2016 debt offering. Such forward-starting interest rate swap agreements were designated as hedges of the cash flows associated with benchmark interest rates underlying future interest payments on the June 2016 debt issuances.

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Index to Consolidated Financial Statements

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LAM RESEARCH CORPORATION

CONSOLIDATED STATEMENTS OF OPERATIONS

(in thousands, except per share data)

See Notes to Consolidated Financial Statements

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LAM RESEARCH CORPORATION

CONSOLIDATED STATEMENTS OF COMPREHENSIVE INCOME

(in thousands)

See Notes to Consolidated Financial Statements

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LAM RESEARCH CORPORATION

CONSOLIDATED BALANCE SHEETS

(in thousands, except per share data)

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None.

Design of Disclosure Controls and Procedures and Internal Control over Financial Reporting

We maintain disclosure controls and procedures and internal control over final reporting that are designed to comply with Rule 13a-15 of the Exchange Act. In designing and evaluating the controls and procedures associated with each, management recognizes that any controls and procedures, no matter how well designed and operated, can provide only reasonable assurance of achieving the desired control objectives and that the effectiveness of controls cannot be absolute because the cost to design and implement a control to identify errors or mitigate the risk of errors occurring should not outweigh the potential loss caused by the errors that would likely be detected by the control. Moreover, we believe that a control system cannot be guaranteed to be 100% effective all of the time. Accordingly, a control system, no matter how well designed and operated, can provide only reasonable, not absolute, assurance that the control system’s objectives will be met.

Disclosure Controls and Procedures

As required by Rule 13a-15(b) under the Securities Exchange Act of 1934, as amended (the “Exchange Act”), as of June 30, 2019, we carried out an evaluation, under the supervision and with the participation of our management, including our Chief Executive Officer and our Chief Financial Officer, of the effectiveness of the design and operation of our disclosure controls and procedures as defined in Rule 13a-15(e). Based upon that evaluation, our Chief Executive Officer and our Chief Financial Officer each concluded that our disclosure controls and procedures are effective, as of June 30, 2019, at the reasonable assurance level.

We intend to review and evaluate the design and effectiveness of our disclosure controls and procedures on an ongoing basis and to correct any material deficiencies that we may discover. Our goal is to ensure that our senior management has timely access to material information that could affect our business.

Changes in Internal Control over Financial Reporting

There has been no change in our internal control over financial reporting during our most recent fiscal quarter that has materially affected, or is reasonably likely to materially affect, our internal control over financial reporting.

Management’s Report on Internal Control over Financial Reporting

Management is responsible for establishing and maintaining adequate “internal control over financial reporting”, as that term is defined in Exchange Act Rules 13a-15(f) and 15d-15(f). Management conducted an evaluation of the effectiveness of internal control over financial reporting based on the framework in Internal Controls — Integrated Framework used by the Committee of Sponsoring Organizations of the Treadway Commission (2013 Framework). Based on that evaluation, management has concluded that the Company’s internal control over financial reporting was effective as of June 30, 2019, at providing reasonable assurance regarding the reliability of financial reporting and the preparation of financial statements for external purposes in accordance with GAAP.

Ernst & Young LLP, an independent registered public accounting firm, audited the financial statements included in this 2019 Form 10-K and has issued an attestation report on the Company’s internal control over financial reporting, as stated in their report, which is included in Part II, Item 8 of this 2019 Form 10-K.

Effectiveness of Controls

While we believe the present design of our disclosure controls and procedures and internal control over financial reporting is effective at the reasonable assurance level, future events affecting our business may cause us to modify our disclosure controls and procedures or internal controls over financial reporting.

None.

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PART III

We have omitted from this 2019 Form 10-K certain information required by Part III because we, as the Registrant, will file a definitive proxy statement with the SEC within 120 days after the end of our fiscal year, pursuant to Regulation 14A, as promulgated by the SEC, for our Annual Meeting of Stockholders expected to be held on or about November 5, 2019, (the “Proxy Statement”), and certain information included in the Proxy Statement is incorporated into this report by reference.

For information regarding our executive officers, see Part I, Item 1 of this 2019 Form 10-K under the caption “Information about our Executive Officers,” which information is incorporated into Part III by reference.

The information concerning our directors required by this Item is incorporated by reference to our Proxy Statement under the heading “Voting Proposals — Proposal No. 1: Election of Directors — 2019 Nominees for Director.”

The information concerning our audit committee and audit committee financial experts required by this Item is incorporated by reference to our Proxy Statement under the heading “Governance Matters — Corporate Governance — Board Committees” and “Governance Matters — Corporate Governance — Board Committees — Audit Committee.”

The Company has adopted a Corporate Code of Ethics that applies to all employees, officers, and directors of the Company. Our Code of Ethics is publicly available on the Investor Relations page of our website at http://investor.lamresearch.com. To the extent required by law, any amendments to, or waivers from, any provision of the Code of Ethics will promptly be disclosed to the public. To the extent permitted by applicable legal requirements, we intend to make any required public disclosure by posting the relevant material on our website in accordance with SEC rules.

The information required by this Item is incorporated by reference to our Proxy Statement under the heading “Compensation Matters — Executive Compensation and Other Information,” “Compensation Matters — CEO Pay Ratio,” and “Governance Matters — Director Compensation.”

The information required by this Item is incorporated by reference to our Proxy Statement under the headings “Stock Ownership — Security Ownership of Certain Beneficial Owners and Management” and “Compensation Matters — Securities Authorized for Issuance Under Equity Compensation Plans.”

The information required by this Item is incorporated by reference to our Proxy Statement under the headings “Audit Matters — Certain Relationships and Related Party Transactions” and “Governance Matters — Corporate Governance — Director Independence Policies.”

The information required by this Item is incorporated by reference to our Proxy Statement under the heading “Audit Matters — Relationship with Independent Registered Public Accounting Firm –– Fees Billed by Ernst & Young LLP” and “Audit Matters –– Relationship with Independent Registered Public Accounting Firm –– Policy on Audit Committee Pre-Approval of Audit and Non-Audit Services.”

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PART IV

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LAM RESEARCH CORPORATION

ANNUAL REPORT ON FORM 10-K

FOR THE FISCAL YEAR ENDED JUNE 30, 2019

EXHIBIT INDEX

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SIGNATURES

Pursuant to the requirements of Section 13 or 15(d) of the Securities Exchange Act of 1934, as amended, the Registrant has duly caused this Report to be signed on its behalf by the undersigned, thereunto duly authorized.

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POWER OF ATTORNEY AND SIGNATURES

By signing this Annual Report on Form 10-K below, I hereby appoint each of Timothy M. Archer and Douglas R. Bettinger, jointly and severally, as my attorney-in-fact to sign all amendments to this Form 10-K on my behalf and to file this Form 10-K (including all exhibits and other related documents) with the Securities and Exchange Commission. I authorize each of my attorneys-in-fact to (1) appoint a substitute attorney-in-fact for himself and (2) perform any actions that he believes are necessary or appropriate to carry out the intention and purpose of this Power of Attorney. I ratify and confirm all lawful actions taken directly or indirectly by my attorneys-in-fact and by any properly appointed substitute attorneys-in-fact.

Pursuant to the requirements of the Securities Exchange Act of 1934, as amended, this Report has been signed below by the following persons on behalf of the Registrant and in the capacities and on the dates indicated.

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